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?2000 integrated device technology, inc. june 2000 dsc-4078/7 1 not recommended for new designs high-speed 3.3v 32k x 16 bank-switchable dual-ported sram with external bank selects features 32k x 16 bank-switchable dual-ported sram architecture ? four independent 8k x 16 banks ? 512 kilobit of memory on chip fast asynchronous address-to-data access time: 15ns user-controlled input pins included for bank selects independent port controls with asynchronous address & data busses four 16-bit mailboxes available to each port for inter- processor communications; interrupt option IDT70V7278S/l notes: 1. the first six address pins for each port serve dual functions. when mbsel = v ih , the pins serve as memory address inputs. when mbsel = v il , the pins serve as mailbox address inputs. 2. each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. refer to truth table i for more details. functional block diagram interrupt flags with programmable masking dual chip enables allow for depth expansion without external logic ub and lb are available for x8 or x16 bus matching lvttl-compatible, single 3.3v (5%) power supply available in a 100-pin thin quad flatpack industrial temperature range (-40 to +85c) is available for selected speeds 8kx16 memory array (bank 3) mux mux r/ w l ce 0l ce 1l ub l lb l oe l i/o 8l-15l i/o 0l-7l a 12l a 0l (1) a 5l (1) a 0l (1) lb l / ub l oe l r/ w l ce l mailbox interrupt logic 8kx16 memory array (bank 1) mux mux 8kx16 memory array (bank 0) mux mux control logic i/o control bank decode address decode r/ w r ce 0r ce 1r ub r lb r oe r i/o 8r-15r i/o 0r-7r a 12r a 0r (1) control logic i/o control bank decode address decode a 5r (1) a 0r (1) lb r / ub r oe r r/ w r ce r 4078 drw 01 mbsel r int r mbsel l int l b ksel 3 (2) b ksel 0 (2) bank select ba 1r ba 0r ba 1l ba 0l ,
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 2 not recommended for new designs description the idt70v7278 is a high-speed 32k x 16 (512k bit) bank- switchable dual-ported sram organized into four independent 8k x 16 banks. the device has two independent ports with separate controls, addresses, and i/o pins for each port, allowing each port to asynchronously access any 8k x 16 memory block not already accessed by the other port. accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. mailboxes are provided to allow inter-processor communications. interrupts are provided to indicate mailbox writes have occurred. an automatic power down feature controlled by the chip enables ( ce 0 and ce 1 ) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. the idt70v7278 offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin thin quad flatpack (tqfp). functionality the idt70v7278 is a high-speed asynchronous 32k x 16 bank- switchable dual-ported sram, organized in four 8k x 16 banks. the two ports are permitted independent, simultaneous access into sepa- rate banks within the shared array. there are four user-controlled bank select input pins, and each of these pins is associated with a specific bank within the memory array. access to a specific bank is gained by placing the associated bank select pin in the appropriate state: v ih assigns the bank to the left port, and v il assigns the bank to the right port (see truth table iv). once a bank is assigned to a particular port, the port has full access to read and write within that bank. each port can be assigned as many banks within the array as needed, up to and including all four banks. the idt70v7278 provides mailboxes to allow inter-processor communications. each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. these mailboxes are external to the common sram array, and are accessed by setting mbsel = v il while setting ce = v ih . each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. the interrupted port can clear the interrupt by reading the upper byte. this read will not alter the contents of the mailbox. if desired, any source of interrupt can be independently masked via software. two registers are provided to permit interpretation of inter- rupts: the interrupt cause register and the interrupt status register. the interrupt cause register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. the information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. the interrupt status register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. truth table v gives a detailed explanation of the use of these registers.
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 3 not recommended for new designs index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1009998 979695 94 9392 9190 8988 8786 8584 8382 81 8079 7877 76 idt70v7278pf pn100-1 (4) 100-pin tqfp top view (5) gnd oe r r/ w r mbsel r ce 1r ce 0r bksel 3 nc gnd a 9r a 10r a 8r a 7r a 6r a 11r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r i/o 15r gnd ub r lb r 4078 drw 02 i/o 15l gnd oe l r/ w l mbsel l ce 1l ce 0l vcc bksel 0 a 11l a 10l nc a 9l a 8l a 7l a 6l i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l ub l lb l gnd i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 0 r i / o 0 l g n d i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r i / o 8 r i / o 9 r i / o 8 l i / o 9 l i / o 6 r a 4 r a 5 l a 4 l a 3 r a 0 r a 1 2 r i n t r i n t l b k s e l 1 a 3 l a 5 r g n d v c c i / o 1 l v c c g n d nc n c b a 0 r b a 1 r a 1 r a 2 r b k s e l 2 g n d n c a 0 l a 1 2 l b a 0 l b a 1 l a 1 l a 2 l nc , pin names notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. notes: 1. duplicated per port. 2. each bank has an input pin assigned that allows the user to toggle the assign- ment of that bank between the two ports. refer to truth table iv for more details. when changing the bank assignment, accesses of the affected banks must be suspended. accesses may continue uninterrupted in banks that are not being reallocated. 3. generated upon mailbox access. 4. all vcc pins must be connected to power supply. 5. all gnd pins must be connected to ground supply. 6. the first six address pins (a 0 -a 5 ) for each port serve dual functions. when mbsel = v ih , the pins serve as memory address inputs. when mbsel = v il , the pins serve as mailbox address inputs (a 6 -a 12 ignored). pin configurations (1,2,3) a 0 - a 12 (1,6) address inputs ba 0 - ba 1 (1 ) bank address inputs mbsel (1) mailbox access control gate bksel 0-3 (2) bank select inputs r/ w (1) read/write enable oe (1 ) output enable ce 0 , ce 1 (1 ) chip enables ub , lb (1) i/o byte enables i/o 0 - i/o 15 (1 ) bidirectional data input/output int (1) interrupt flag (output) (3) v cc (4 ) 3.3vpower gnd (5 ) ground 4078 tbl 01
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 4 not recommended for new designs truth table iii ? mailbox read/write control (1) notes: 1. chip enable references are shown above with the actual ce 0 and ce 1 levels, ce is a reference only. 2. port "a" and "b" references are located where ce is used. 3. "h" = v ih and "l" = v il . 4. ce and mbsel cannot both be active at the same time. truth table i ? chip enable (1,2,3,4) truth table ii ? non-contention read/write control notes: 1. ba 0l - ba 1l ba 0r - ba 1r : cannot access same bank simultaneously from both ports. 2. refer to truth table i. 3. ce and mbsel cannot both be active at the same time. notes: 1. there are four mailbox locations per port written to and read from all the i/o's (i/o 0 -i/o 15 ). these four mailboxes are addressed by a 0 -a 5. refer to truth table v. 2. refer to truth table i. 3. each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to ub and lb appropriately. ce ce 0 ce 1 mode l v il v ih port selected (ttl active) < 0.2v > v cc -0.2v port selected (cmos active) h v ih x port deselected (ttl inactive) xv il port deselected (ttl inactive) > v cc -0.2v x port deselected (cmos inactive) x< 0.2v port deselected (cmos inactive) 4078 tbl 02 inputs (1 ) outputs mode ce (2 ) r/ w oe ub lb mbsel i/o 8-15 i/o 0-7 hxxxxhhigh-zhigh-zdeselected: power-down x (3 ) xxhh x (3 ) hig h-z high-z both bytes de selected llxlhhdata in high-z write to upper byte only l l x h l h high-z data in write to lower byte only llxllhdata in data in write to both bytes lhllhhdata out high-z read upp er byte only lhlhlhhigh-zdata out read lower byte only lhlllhdata out data out read both bytes x (3 ) xhxx x (3 ) high-z high-z outputs disabled 4078 tbl 03 inputs outputs mode ce (2 ) r/ w oe ub lb mbsel i/o 8-15 i/o 0-7 hhl x (3 ) x (3) ldata out data out read data from mailbox, clears interrupt hhlllldata out data out read data from mailbox, clears interrupt hlx l (3) l (3) ldata in data in write data into mailbox lxxxxl ____ ____ not allowed 4078 tbl 04
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 5 not recommended for new designs absolute maximum ratings (1) dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 5%) capacitance (1) (t a = +25c, f = 1.0mhz) tqfp package recommended dc operating conditions maximum operating temperature and supply voltage (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 5% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 5%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 5%. notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv represents the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. 3. c out represents c i/o as well. note: 1. at vcc < 2.0v, input leakages are undefined. symbol rating commercial & industrial unit v term (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 4078 tbl 05 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v3.3v + 5% industrial -40 o c to +85 o c0v3.3v + 5% 4078 tbl 06 symbol parameter min. typ. max. unit v cc supply voltage 3.135 3.3 3.465 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc +5% (2 ) v v il input low voltage -0.3 (1 ) ____ 0.8 v 4078 tbl 07 symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out (3 ) output capacitance v out = 3dv 10 pf 4078 tbl 08 symbol parameter test conditions 70v7278s 70v7278l unit min. max. min. max. |i li | input leakage current (1) v cc = 3.465v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , mbsel = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 4078 tb l 09
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 6 not recommended for new designs dc electrical characteristics over the operating temperature and supply voltage range (1,6) (v cc = 3.3v 5%) notes: 1. 'x' in part numbers indicates power rating (s or l). 2. v cc = 3.3v, t a = +25c, and are not production tested. i ccdc = 120ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc, and using ?ac test conditions? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". 6. refer to truth table i. 70v7278x15 com'l only 70v7278x20 com'l only 70v7278x25 com'l & ind symbol parameter test condition version typ. (2) max. typ. (2) max. typ. (2) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled mbsel = v ih f = f max (3 ) com'l s l 200 200 280 230 170 170 260 210 160 160 250 200 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ 160 160 280 230 i sb1 standby current (bo th ports - ttl level inputs) ce l = ce r = v ih mbsel r = mbsel l = v ih f = f max (3 ) com'l s l 50 50 85 60 40 40 75 50 35 35 70 45 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ 35 35 80 55 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (3) mbsel r = mbsel l = v ih com'l s l 120 120 160 140 100 100 140 120 90 90 130 110 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ 90 90 150 130 i sb3 full standby current (both ports - all cmos level inputs) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4 ) mbsel r = mbsel l > v cc - 0.2v com'l s l 1.5 1.5 6 3 1.5 1.5 6 3 1.5 1.5 6 3 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ 1.5 1.5 10 6 i sb4 full standby current (one port - all cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) mbsel r = mbsel l > v cc - 0.2v v in > v cc - 0.2v o r v in < 0.2v active port outputs disabled f = f max (3 ) com'l s l 115 115 140 125 95 95 130 110 85 85 120 100 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ 85 85 140 120 4078 tbl 10
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 7 not recommended for new designs ac test conditions figure 3. lumped capacitance load typical derating curve notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and mbsel = v ih . to access mailbox, ce = v ih and mbsel = v il . 4. 'x' in part numbers indicates power rating (s or l). 5. refer to truth table i. ac electrical characteristics over the operating temperature and supply voltage range (4) figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig. input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1,2 and 3 4078 tbl 11 4078 drw 04 590 ? 30pf 435 ? 3.3v data out int 590 ? 5pf* 435 ? 3.3v data out 4078 drw 03 , ? t ace /t aa ( typical, ns) 4078 drw 05 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 capacitance (pf) -1 0 - 10pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance , 70v7278x15 com'l only 70v7278x20 com'l only 70v7278x25 com'l & ind unit symbol parameter min.max.min.max.min.max. read cycle t rc re ad cycle time 15 ____ 20 ____ 25 ____ ns t aa address access time ____ 15 ____ 20 ____ 25 ns t ace chip enable access time (3) ____ 15 ____ 20 ____ 25 ns t abe byte enable access time (3) ____ 15 ____ 20 ____ 25 ns t aoe output enable access time ____ 9 ____ 10 ____ 11 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 8 ____ 9 ____ 10 ns t pu chip enab le to power up time (2,5) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2,5) ____ 15 ____ 20 ____ 25 ns t mop mailbox flag update pulse ( oe or mbsel )10 ____ 10 ____ 10 ____ ns t maa mailbox address access time ____ 15 ____ 20 ____ 25 ns 4078 tbl 12
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 8 not recommended for new designs notes: 1. bank 0 refers to the first 8kx16 memory spaces, bank 1 to the second 8kx16 memory spaces, bank 2 to the third 8kx16 memory spaces, and bank 3 to the fourth 8kx16 memory spaces. 'left' indicates the bank is assigned to the left port; 'right' indicates the bank is assigned to the right port. 0-4 banks may be assigned to either port. 2. the bank select pin inputs must be set at either v ih or v il - these inputs are not tri- statable. when changing the bank assignments, accesses of the affected banks must be suspended. accesses may continued uninterrupted in banks that are not being reallocated. 3. 'h' = v ih , 'l' = v il , 'x' = don't care. assigning the banks via the external bank selects there are four bank select pins available on the idt70v7278, and each of these pins is associated with a specific bank within the memory array. the pins are user-controlled inputs: access to a specific bank is assigned to a particular port by setting the input to the appropriate level. the process of assigning the banks is detailed in truth table iv. once a bank is assigned to a port, the owning port has full access to read and write within that bank. the opposite port is unable to access that bank until the user reassigns the port. access by a port to a bank truth table iv ? memory bank assignment ( ce = v ih ) (2,3) mailbox interrupts and interrupt control registers if the user chooses the mailbox interrupt function, four mailbox locations are assigned to each port. these mailbox locations are external to the memory array. the mailboxes are accessed by taking mbsel low while holding ce high. the mailboxes are 16 bits wide and controllable by byte: the message is user-defined since these are addressable sram locations. an interrupt is generated to the opposite port upon writing to the upper byte of any mailbox location. a port can read the message it has just written in order to verify it: this read will not alter the status of the interrupt sent to the opposite port. the interrupted port can clear the interrupt by reading the upper byte of the applicable mailbox. this read will not alter the contents of the mailbox. the use of mailboxes to generate interrupts to the opposite port and the reading of mailboxes to clear interrupts is detailed in truth table v. if desired, any of the mailbox interrupts can be independently masked via software. masking of the interrupt sources is done in the mask register. the masks are individual and independent: a port can mask any combination of interrupt sources with no effect on the other sources. each port can modify only its own mask register. the use of this register is detailed in truth table v. two registers are provided to permit interpretation of interrupts: these are the interrupt cause register and the interrupt status register. the interrupt cause register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to by the opposite port. the information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. the interrupt status register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. the use of the interrupt cause register and the interrupt status register is detailed in truth table v. which it does not control will have no effect if written, and if read unknown values on d 0 -d 15 will be returned. each port can be assigned as many banks within the array as needed, up to and including all four banks. the bank select pin inputs must be set at either v ih or v il - these inputs are not tri-statable. when changing the bank assignments, accesses of the affected banks must be suspended. accesses may continue uninterrupted in banks that are not being reallocated. bksel0 bksel1 bksel2 bksel3 bank and direction (1) h x x x bank 0 left x h x x bank 1 left x x h x bank 2 left x x x h bank 3 left l x x x bank 0 right x l x x bank 1 right x x l x bank 2 right x x x l bank 3 right 4078 tbl 1 3
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 9 not recommended for new designs truth table v ? mailbox interrupts ( ce = v ih ) (8,9) notes: 1. there are four independent mailbox locations available to each side, external to the standard memory array. the mailboxes can be written to in either 8-bit or 16-bit widths. the upper byte of each mailbox has an associated interrupt to the opposite port. the mailbox interrupts can be individu ally masked if desired, and the status of the interrupt determined by polling the interrupt status register (see note 6 for this table). a port can read its own mailboxe s to verify the data written, without affecting the interrupt which is sent to the opposite port. 2. these registers allow a port to read the data written to a specific mailbox location by the opposite port. reading the upper byte of the data in a particular mailbox clears the interrupt associated with that mailbox without modifying the data written. once the address and r/ w are stable, the actual clearing of the interrupt is triggered by the transition of mbsel from v ih to v il . 3. this register contains the mask register (bits d 0 -d 3 ), the interrupt cause register (bits d 4 -d 7 ), and the interrupt status register (bits d 8 -d 11 ). the controls for r/ w , ub , and lb are manipulated in accordance with the appropriate function. see notes 4, 5, and 6 for this table. bits d 12 -d 15 are "don't care". 4. this register, the mask register, allows the user to independently mask the various interrupt sources. writing v ih to the appropriate bit (d 0 = mailbox 0, d 1 = mailbox 1, d 2 = mailbox 2, and d 3 = mailbox 3) disables the interrupt, while writing v il enables the interrupt. all four bits in this register must be written at the same time. this register can be read at any time to verify the mask settings. the masks are individual and independent: any single interrupt s ource can be masked with no effect on the other sources. each port can modify only its own mask settings. 5. this register, the interrupt cause register, gives the user a snapshot of what has caused the interrupt to be generated. reading v ol for a specific bit (d 4 = mailbox 0, d 5 = mailbox 1, d 6 = mailbox 2, and d 7 = mailbox 3) indicates that the associated interrupt source has generated an interrupt. acknowledging the interrupt clears the bit in this register (see note 2 for this table). this register provides post-mask information: if the interrupt source has been maske d, the associated bit in this register will not update. 6. this register, the interrupt status register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardl ess of whether they have been masked. reading v ol for a specific bit (d 8 = mailbox 0, d 9 = mailbox 1, d 10 = mailbox 2, and d 11 = mailbox 3) indicates that the associated interrupt source has generated an interrupt. acknowledging the interrupt clears the associated bit in this register (see note 2 for this table). thi s register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this register will update. 7. access to registers defined as "reserved" will have no effect, if written, and if read unknown values on d 0 -d 15 will be returned. 8. these registers are not guaranteed to initialize in any known state. at power-up, the initialization sequence should include the set-up of these registers. 9. 'l' = v il or v ol , 'h' = v ih or v oh , 'x' = don't care. mb sel r/ w ub lb a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 description l xxxllllll r eserved (7) reserved (7) lxxx reserved (7) reserved (7) l(1)(1)(1)hlllllx xxxxxxxxx x x x x x x mailbox 0 - set inte rrupt on opposite port l(1)(1)(1)hllllhx xxxxxxxxx x x x x x x mailbox 1 - set inte rrupt on opposite port l (1)(1)(1)hlllhlxxxxxxxxxx x x x x x x mailbox 2 - set inte rrupt on opposite port l (1)(1)(1)hlllhhxxxxxxxxxx x x x x x x mailbox 3 - set inte rrupt on opposite port h(2)(2)hllhllxxxxxxxxxx x x x x x x mailbox 0 - clear opposite port inte rrupt h(2)(2)hllhlhxxxxxxxxxx x x x x x x mailbox 1 - clear opposite port inte rrupt h(2)(2)hllhhlxxxxxxxxxx x x x x x x mailbox 2 - clear opposite port inte rrupt h(2)(2)hllhhhxxxxxxxxxx x x x x x x mailbox 3 - clear opposite port inte rrupt l (3) (3) (3) h l h l l l (4) (4) (4) (4) (5) (5) (5) (5) (6) (6) (6) (6) x x x x mailbox interrupt controls lxxx reserved (7) reserved (7) l x xxhhhhhh r eserved (7) reserved (7) 4078 tbl 14
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 10 not recommended for new designs waveform of read cycles (4) timing of power-up power-down ce 4078 drw 07 t pu i cc i sb t pd 50% 50% (5) , notes: 1. timing depends on which signal is asserted last, ce , oe , lb , or ub . 2. timing depends on which signal is de-asserted first ce , oe , lb , or ub . 3. start of valid data depends on which timing becomes effective last: t aoe , t ace , t aa , or t abe . 4. mbsel = v ih . 5. refer to truth table i. t rc r/ w ce addr t aa oe ub , lb 4078 drw 06 (3) t ace (3) t aoe (3) t abe (3) (1) t lz t oh (2) t hz data out valid data (3) (5)
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 11 not recommended for new designs notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and mbsel = v ih . to access mailbox, ce = v ih and mbsel = v il . either condition must be valid for the entire t ew time. refer to truth tables i and iii. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part numbers indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage (5) symbol parameter 70v7278x15 com'l only 70v7278x20 com'l only 70v7278x25 com'l & ind unit min. max. min. max. min. max. write cycle t wc write cycle time 15 ____ 20 ____ 25 ____ ns t ew chip enable to end-of-write (3 ) 12 ____ 15 ____ 20 ____ ns t aw address valid to end-of-write 12 ____ 15 ____ 20 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t bs bank set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 12 ____ 15 ____ 20 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ 20 ____ ns t hz output high-z time (1,2) ____ 8 ____ 9 ____ 10 ns t dh data hold time (4) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 8 ____ 9 ____ 10 ns t ow output active from end-of-write (1 , 2 ,4 ) 3 ____ 3 ____ 3 ____ ns t mwrd mailbox write to read time 5 ____ 5 ____ 5 ____ ns 4078 tbl 1 5
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 12 not recommended for new designs timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) notes: 1. r/ w or ce or ub and lb must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or mbsel or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or mbsel low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 2). 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and mbsel = v ih . to access mailboxes, ce = v ih and mbsel = v il . t ew must be met for either condition. 10. refer to truth table i. timing waveform of write cycle no. 2, ce , ub , lb controlled timing (1,5) r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (7) ub or lb 4078 drw 08 (9) ce or mbsel (9,10) (7) (3) t lz valid (4) 4078 drw 09 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub or lb (3) (2) (6) ce or mbsel (9,10) (9)
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 13 not recommended for new designs timing waveform of mailbox read after write timing, either side (1,2) notes: 1. ce = v ih for the duration of the above timing (both write and read cycle), refer to truth table i. 2. ub and lb are controlled as necessary to enable the desired byte accesses. mbsel 4078 drw 11 t aw t ew t mop i/o 0-15 valid address t maa r/ w t wr t oh t ace valid address data in valid data out valid t dw t wp t dh t as t mwrd t aoe read cycle write cycle a 0 -a 5 oe , timing waveform of left port write to right port read of same data (1,2,3) notes: 1. ub and lb are controlled as necessary to enable the desired byte accesses. 2. timing for right port write to left port read is identical. 3. refer to truth table i and iv. bksel 0-3 4078 drw 10 t wc i/o 0l-15l addresses match data in valid data out valid read cycle write cycle ce l a 0l-12l and a 0r-12r ce r i/o 0r-15r r/ w r oe r t as t wp t aw t ew t dw t dh t wr t bs t lz t ace t hz t oh r/ w l
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 14 not recommended for new designs waveform of interrupt timing (1,5) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposi te from port ?a?. 2. see interrupt truth table v. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 5. refer to truth table i. notes: 1. 'x' in part numbers indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (1) 4078 drw 12 addr "a" mailbox set address mbsel "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 4078 drw 13 addr "b" mailbox clear address mbsel "b" oe "b" t as t rc (3) t inr (3) int "b" (2) 70v7278x15 com'l only 70v7278x20 com'l only 70v7278x25 com'l & ind symbol parameter min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins inte rrup t se t time ____ 15 ____ 20 ____ 25 ns t inr interrupt reset time ____ 15 ____ 20 ____ 25 ns 4078 tb l 16
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 15 not recommended for new designs depth and width expansion the idt70v7278 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v7278 can also be used in applications requiring 4078 drw 14 idt70v7278 bank-switchable sram ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 13 ce 1 ce 0 v cc v cc idt70v7278 bank-switchable sram idt70v7278 bank-switchable sram idt70v7278 bank-switchable sram control inputs control inputs control inputs control inputs bksel 0-3 r/ w lb , ub oe , figure 4. depth and width expansion with idt70v7278 expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications.
6.42 IDT70V7278S/l 32k x 16 3.3v bank-switchable dual-ported sram with external bank selects industrial and commercial temperature ran ges 16 not recommended for new designs ordering information a power 999 speed a package a process/ temperature range blank i commercial (0 cto+70 c) industrial (-40 cto+85 c) pf 100-pin tqfp (pn100-1) 15 20 25 s l standard power low power xxxxx device type 512kbit (4 x 8k x 16) 3.3v bank-switchable dual-ported sram with external bank selects 70v7278 idt 4078 drw 15 commercial only commercial & industrial commercial & industrial speed in nanoseconds , the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 3/5/99: initiated datasheet document history converted to new format cosmetic typographical corrections page 3 added additional notes to pin configurations added 15ns speed grade 6/10/99: changed drawing format 9/1/99: removed preliminary 3/10/00: added industrial temperature ranges and removed corresponding notes replaced idt logo page 1 added industrial temperature note changed 200mv to 0mv in notes 6/8/00: page 5 increated storage temperature parameter clarified t a parameter page 6 dc electrical parameters?changed wording from "open" to "disabled" corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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